Wafer level packaging (WLP) technology provides for the packaging of semiconductor devices at a wafer level. WLP is employed in a variety of technologies including 3D-integrated circuits (IC), chip scale package (CSP) devices, and micro-electro-mechanical systems (MEMS). Potential advantages of using WLP technology include enhancing electrical properties, providing for increased density, reducing device sizes, reducing costs, and allowing for additional testing at wafer level. However, there are several limitations to the current WLP technology and the integration of the wafer fabrication and packaging processes it provides. The methods of packaging (e.g., protecting the device and providing interconnections to the outside world) may not be compatible with the fabrication processes that are used to form the devices. For example, certain bonding materials have not been compatible with some fabrication processes (e.g., complementary metal-oxide semiconductor (CMOS)). Furthermore, prior WLP solutions have been limited to capping thin MEMS layers, have increased leakage pathways, and have disadvantageous bonding effects.